China is strictly abiding by Moore’s Law and the main chip release cycle of approximately one year adopted by companies such as Intel, AMD, and Nvidia.
The Chinese Academy of Sciences, which is developing an open source RISC-V performance processor supported by the government, said it will release major design upgrades every six months. CAS hopes that the accelerated release of chip designs can build momentum and support for its open source projects.
RISC-V is based on an open source instruction architecture and is royalty-free, which means companies can adopt designs without paying license fees.
The first Xiangshan chip of the Chinese Academy of Sciences, called Yanqi Lake, was taped out in July 2021. Its successor, Nanhu, announced a major performance and architecture upgrade on Monday and will be listed in early 2022.
Bao Yungang, a professor at the Institute of Computing Technology of the Chinese Academy of Sciences, said in a speech at the RISC-V conference: “For us, we want to create a startup company to commercialize, but we hope that there are other companies that can do so.” San Francisco summit.
“We hope to see companies like Red Hat on RISC-V,” Yungang said.
China has made the development of local chips a national priority to catch up with the United States. China also supports chips designed and manufactured by ARM, and ARM charges licensing fees for its intellectual property rights.Alibaba has deploy The RISC-V server chip has open sourced some designs in its cloud service.
The six-month release cycle is related to the acceleration of the approval of new features by the RISC-V Foundation that created the ISA.
Mark Himelstein, CTO of RISC-V International, said in an interview with The Register: “The one thing that really needs to be aware of is that we approved the zero specification in 2020. In 2021 we have done 16 items, including some like Vector is such a big thing.” Monday.
Compared with SiFive’s P550, the first Xiangshan chip called Yanqihu is regarded as the mainstream computing competitor of the ARM Cortex-A76 core. Yanqi Lake is optimized for the 28-nanometer process.
The new Xiangshan chip named Nanhu is specially designed for the 14-nanometer process, and is ostensibly made of minimum wage. It is based on the 64-bit RV64GCBK design, with BK logo to support new extensions.
In view of the collaborative nature of RISC-V, some of Nanhu’s new features have borrowed from SiFive designs, such as Block contains cache.
In the slide, the Nanhu chip is twice as fast as its predecessor in the benchmark test on SPEC2006 everywhere. The new dual-core chip is designed to operate at 2.0GHz, while the single-core frequency of the previous-generation chip is 1.3GHz.
The design revised the front-end and back-end designs to improve throughput and performance. In his speech, Yungang said that the goal is “to achieve higher branch prediction accuracy and higher read throughput.”
The new architecture optimizes the execution unit and supports more instructions, including bit operations and scalar encryption extensions.
“Now it also supports command fusion in common cases,” Yungang said.
It also has a floating-point unit that complies with the IEEE754 standard, called Fudian.
For load storage units, new features are supported, including custom and configurable physical memory attributes, physical memory protection, and ECC for all three-level caches (L1, L2, L3). Yungang said that the IPC (instructions per cycle) of the memory-sensitive benchmark has increased by 30%. ®
